Configurable real-time trace port for embedded processors

Filing Information

• Publication Number: US20040250164
• Application Number: US10444918
• Filing date: 05/22/2003
• Publication date: 12/09/2004
• Predicted expiration date: 05/22/2023

• U.S. Classifications: 714/30  ·
• International Classifications: H02H003/05 ·
• View document at: (opens new window):
  USPTO  ·  PAIR  ·  esp@cenet  ·  Patent Family

Patent Family

Abstract

An embedded processor having a programmable trace port that selectively limits the amount of trace information passed from the processor core to an output buffer, and selectively controls the rate at which the trace information is output from the output buffer to an off-chip debug system. A configurable on-chip filter circuit selectively passes data and program information based on a wide range of user-defined combinations and/or sequences of trigger events (e.g., instruction addresses/types or data addresses/values). The filtered trace information is then compressed using separate data and program compression circuits, and passed to separate data and program output buffer. The data output buffer includes an adjustable read (output) rate (e.g., one-half or one-quarter of the processor core clock cycle), and allows a user to select between one or two output pointers.

Independent Claims | See all claims (23)

1. 1. An embedded processor comprising: a processor core for executing a program instruction associated with an instruction word transmitted on an instruction bus, and for transmitting a corresponding data word on a data bus in response to the executed program instruction; and a trace port circuit including: a configurable filter circuit coupled to the instruction bus and the data bus for selectively passing at least a portion of the instruction word and the corresponding data word when at least one of the instruction word and the corresponding data word satisfies a user-defined trigger event; a compression circuit for compressing said at least one of the instruction word and the corresponding data word passed from the configurable filter circuit; and an output buffer for temporarily storing the compressed instruction word and compressed data word.