Filing Information

Inventor(s)	Dhiraj Kumar Pradhan · Jawar Singh · Jimson Mathew ·
Assignee(s)	The University of Bristol ·  View assignee updates
Correspondent	ALSTON & BIRD LLP ·
Application Number	US12120980
Filing date	05/15/2008
Publication date	11/19/2009
Predicted expiration date	05/15/2028
U.S. Classifications	365/156  · 365/189.011  ·
International Classifications	G11C1100  · G11C700  ·
Kind Code	A1

Patent Family

Abstract

A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground.

Independent Claims | See all claims (14)

1. 1. A static random access memory comprising: a. a pair of inverters each having an input and an output; b. a cross-coupling path coupling the input of a first one of the inverters to the output of a second one of the inverters; and c. a transmission gate comprising: i. a p-channel transistor coupling the input of the second one of the inverters to the output of the first one of the inverters; and ii. an n-channel transistor coupling the input of the second one of the inverters to the output of the first one of the inverters in parallel with the p-channel transistor.
2. 8. A method of operating a static random access memory, the memory comprising: a. a pair of inverters each having an input and an output; b. a cross-coupling path coupling the input of a first one of the inverters to the output of a second one of the inverters; and c. a transmission gate comprising: i. a p-channel transistor coupling the input of the second one of the inverters to the output of the first one of the inverters; and ii. an n-channel transistor coupling the input of the second one of the inverters to the output of the first one of the inverters in parallel with the p-channel transistor, the method comprising: switching the transistors of the transmission gate from an ON state to an OFF state to disconnect the input of the second one of the inverters from the output of the first one of the inverters; accessing the memory with the transistors of the transmission gate in the OFF state; and switching the transistors of the transmission gate from the OFF state to the ON state after the access operation in order to reconnect the input of the second one of the inverters to the output of the first one of the inverters.
3. 9. A static random access memory comprising: a. a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; b. a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and c. a switch for selectively connecting and disconnecting the ground node of the second inverter to and from ground.
4. 13. A method of operating a static random access memory, the memory comprising a pair of cross-coupled inverters each having a supply voltage node connected to a supply voltage, and a ground node connected to ground, the method comprising disconnecting the ground node of one of the inverters from ground during a write operation.