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US4745082: Method of making a self-aligned MESFET using a substitutional gate with side walls

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Filing Information

Inventor(s) Siang P. Kwok ·
Assignee(s) Ford Microelectronics, Inc. ·
Attorney/Agent(s) Brooks & Kushman ·
Primary Examiner Brian E. Hearn ·
Assistant Examiner William Bunch ·
Application Number US6873515
Filing date 06/12/1986
Issue date 05/17/1988
Predicted expiration date 06/12/2006
U.S. Classifications 437/39  · 437/44  ·
International Classifications H01L 21306  ·
Kind CodeA
International Classifications 29571;576 B;578;579;591 ·
22 Claims, No Drawings


Abstract

A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device. This technique is especially useful in the production of Group III-V compound semiconductors, particularly gallium arsenide semiconductors.

Independent Claims | See all claims (22)

  1. 1. A process for producing a semiconductor device, comprising:a. depositing a layer of insulator material onto a supporting substrate of the type having a surface and which includes a channel region below the surface containing a carrier concentration of a desired conductivity type;b. removing selected portions of the insulator material to form a substitutional gate on the substrate surface;c. forming sidewalls of a dielectric material selected from the group consisting of silicon dioxide, silicon nitride, polymers and photoresist bounding the substitutional gate to define an effective masking area in cooperation with the substitutional gate;d. reducing the thickness of the sidewalls to a desired thickness;e. ion implanting a dopant into the unmasked region of the substrate;f. removing the sidewalls;g. annealing the resultant device;h. applying a planarizing polymeric material over the substrate surface and the substitutional gate and thereafter etching back to expose the top of the substitutional gate;i. removing the substitutional gate;j. depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate; andk. depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device.
  2. 22.22. A process for producing a semiconductor device comprising:a. depositing a layer of silicon dioxide to a thickness of about 4000 to 15,000 angstroms onto a supporting gallium arsenide substrate having a surface and including a channel region below the surface which contains a carrier concentration of an n-type conductivity;b. removing portions of the silicon dioxide to form a substitutional gate on the surface;c. forming sidewalls of a dielectric material selected from the group consisting of silicon dioxide, silicon nitride, polymers and photoresists bounding the substitutional gate by depositing a layer of silicon nitride to a thickness of about 2000 angstroms and removing selected portions by etching to form sidewalls sufficiently thick to perform ion implantation blockage;d. reducing the thickness of the sidewalls to a desired thickness;e. ion implanting an n+ type dopant into the unmasked region of the substrate;f. removing the sidewalls from the substitutional gate by preferentially etching the sidewalls without etching the substitutional gate;g. capless annealing for about two minutes under arsine overpressure at about 800.degree. to 900.degree. Celsius to prevent arsenic evaporation;h. applying a planarizing polymeric material over the substrate surface and the substitutional gate and thereafter etching back to expose the top of the substitutional gate;i. removing the substitutional gate by applying buffered hydrofluoric acid to the substitutional gate;j. depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate; andk. depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device.

References Cited

U.S. Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
US4334349 Tokyo Shibaura Denki Kabushiki Kaisha Aoyama et al. Jun 1982
US4351099 Matsushita Electronics Corporation Takagi et al. Sep 1982
US4503599 Ltd. Hitachi Ueyanagi et al. Mar 1985
US4505023 The United States of America as represented by the Secretary of the Navy Tseng et al. Mar 1985
US4532004 Kabushiki Kaisha Toshiba Akiyama et al. Jul 1985
US4546540 Ltd. Hitachi Ueyanagi et al. Oct 1985
US4561169 Ltd. Hitachi Miyazaki et al. Dec 1985
US4569119 Kabushiki Kaisha Toshiba Terada et al. Feb 1986

Other Publications

Yamasaki et al., "GaAs LSI-Directed MESFET's with Self-Aligned . . . ", IEEE Trans. on Elect. Devices, vol. 29, No. 11, Nov. 1982, pp. 1772-1777.

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