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US5268333: Method of reflowing a semiconductor device

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Filing Information

Inventor(s) Sung-Min Lee · Yoo-suck Jung ·
Assignee(s) Samsung Electronics Co., Ltd. ·
Attorney/Agent(s) Cushman Darby & Cushman ·
Primary Examiner Brian E. Hearn ·
Assistant Examiner Tuan Nguyen ·
Application Number US7772870
Filing date 10/08/1991
Issue date 12/07/1993
Predicted expiration date 10/08/2011
U.S. Classifications 437/235  · 437/228  ·
International Classifications H01L 2102  ·
Kind CodeA
International Classifications 437235;236;982;240;228 ·
Foreign Priority KR9021056 - 12/19/1990 ·
18 Claims, No Drawings


Abstract

A method of reflowing a semiconductor device to increase the planarization thereof includes the steps of first forming a first insulating layer over a silicon semiconductor substrate, forming at least one electrode over the first insulating layer, and then forming a second insulating layer over the at least one electrode and the first insulating layer. A first borophospho silicate glass (BPSG) layer of low concentration is then formed over the resultant surface to a thickness of 6000 to 9000 .ANG. and containing 3-4 wt. % boron and 5-7 wt. % phosphorous. A second borophospho silicate glass (BPSG) layer of high concentration is formed over the resultant surface of the first borophospho silicate glass (BPSG) layer to a thickness of 2000 to 6000 .ANG. and containing 4-7 wt. % boron and 8-10 wt. % phosphorous. This resultant structure is then exposed to a reflowing process so as to flatten the respective surfaces of the first and second borophospho silicate glass (BPSG) layers to form a planarized resultant structure which is then etched. The use of two different concentrations of BPSG films permits lowering baking temperatures during the reflow process by as much as 50.degree. C. while preventing the corrosive forming properties of the resultant reflowed BPSG film.

Independent Claims | See all claims (18)

  1. 1. A method of reflowing a semiconductor device comprising the steps of:forming a first insulating layer over a semiconductor substrate;forming at least one electrode over said first insulating layer;forming a second insulating layer over said at least one electrode and said first insulating layer;forming a first borophospho silicate glass (BPSG) layer of first concentration over the resultant surface of said second insulating layer, said first concentration being a low concentration containing about 3-4 wt. % boron and about 5-7 wt. % phosphorous;forming a second borophospho silicate glass (BPSG) layer of second concentration over the resultant surface of said first borophospho silicate glass (BPSG) layer, said second concentration being a high concentration containing about 4-7 wt. % boron and about 8-10 wt. % phosphorous;exposing the resultant structure to a reflowing process so as to flatten the respective surfaces of said first and second borophospho silicate glass (BPSG) layers to form a planarized resultant structure; andetching said second borophospho silicate glass (BPSG) layer of said planarized resultant structure to expose the first borophospho silicate glass (BPSG) layer.
  2. 18.18. A method of reflowing a semiconductor device comprising the steps of:forming a first insulating layer over a silicon semiconductor substrate;forming at least one electrode over said first insulating layer;forming a second insulating layer over said at least one electrode and said first insulating layer;forming a first borophospho silicate glass (BPSG) layer of low concentration over the resultant surface of said second insulating layer to a thickness in a range from about 6000 to 9000 .ANG., said low concentration containing about 3-4 wt. % boron and about 5-7 wt. % phosphorous;forming a second borophospho silicate glass (BPSG) layer of high concentration over the resultant surface of said first borophospho silicate glass (BPSG) layer to a thickness in a range from about 2000 to 6000 .ANG., said high concentration containing about 4-7 wt. % boron and about 8-10 wt. % phosphorous;exposing the resultant structure to a reflowing process so as to flatten the respective surfaces of said first and second borophospho silicate glass (BPSG) layers to form a planarized resultant structure, said step of exposing the resultant structure to a reflowing process comprising the step of exposing said resultant structure to one of a nitrogen environment at a temperature of about 800.degree.-850.degree. C. and a vapor environment at a temperature of about 750.degree.-800.degree. C. for approximately thirty minutes to flatten the planarized resultant structure to an angle .THETA. which is less than about 10.degree.; andanisotropically dry etching said second borophospho silicate glass (BPSG) layer of said planarized resultant structure down to the surface of said first borophospho silicate glass (BPSG) layer and then partially etching said first borophospho silicate glass (BPSG) layer.

References Cited

U.S. Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
US4492717 International Business Machines Corporation Pliskin et al. Jan 1985
US4546016 RCA Corporation Kern Oct 1985
US4903117 Mitsubishi Denki Kabushiki Kaisha Okamoto et al. Feb 1990
US4948743 Matsushita Electronics Corporation Ozaki Aug 1990
US5004704 Kabushiki Kaisha Toshiba Maeda et al. Apr 1991
US5094984 Hewlett-Packard Company Liu et al. Mar 1992
US5166101 Applied Materials, Inc. Lee et al. Nov 1992

Other Publications

Susa et al., "Borophosphosilicate glass flow in a PH.sub.3 -O.sub.2 ambient", J. Electrochem. Soc., Solid State Science and Technology, vol. 133, No. 7, Jul. 1986, pp. 1517-1518.

Referenced By

Document NumberAssigneeInventorsIssue/Pub Date
DE19648082 HYUNDAI ELECTRONICS IND PARK IN-OK et al. May 1997
GB2307344 HYUNDAI ELECTRONICS IND PARK IN-OK et al. May 1997
EP0766291 TEXAS INSTRUMENTS INCORPORATED Somnath S. Nag et al. Apr 1997
US6468922 Oki Electric Industry Co., Ltd. Syoji Yoh Oct 2002
US6492282 Siemens Aktiengesellschaft Dirk Tobben et al. Dec 2002
US6620534 Micron Technology, Inc. Gurtei Sandhu et al. Sep 2003
US6734564 International Business Machines Corporation John Edward Cronin et al. May 2004
US6924555 International Business Machines Corporation John Edward Cronin et al. Aug 2005
US7955993 Taiwan Semiconductor Manufacturing Co., Ltd. Chin Kun Lan et al. Jun 2011
US8486820 --
US5770469 Lam Research Corporation Kevin J. Uram et al. Jun 1998
US6169026 Hyundai Electronics Industries Co., Ltd. In Ok Park et al. Jan 2001
US5880039 Hyundai Electronics Industries Co., Ltd. Sahng Kyoo Lee Mar 1999
US5963837 Siemens Aktiengesellschaft Matthias Ilg et al. Oct 1999
US6200849 Samsung Electronics Co., Ltd. Yun Gi Kim Mar 2001
US5946591 Texas Instruments Incorporated Shigeo Ashigaki et al. Aug 1999
US5804515 Hyundai Electronics Industries, Co., Ltd. Sang Kyun Park Sep 1998
US6319848 Texas Instruments Incorporated Andrej Litwin et al. Nov 2001
US6204196 Micron Technology, Inc. Gurtej Sandhu et al. Mar 2001
US5444026 Samsung Electronics Co., Ltd. Chang-kyu Kim et al. Aug 1995
US5930674 Mitsubishi Denki Kabushiki Kaisha Isao Tottori Jul 1999
US5656556 Vanguard International Semiconductor Fu-Liang Yang Aug 1997
US5773361 International Business Machines Corporation John Edward Cronin et al. Jun 1998

Patent Family

Document NumberAssigneeInventorsIssue/Pub Date
DE4133625 SAMSUNG ELECTRONICS CO LTD LEE SUNG-MIN et al. Jul 1992
US5268333 Samsung Electronics Co., Ltd. Sung-Min Lee et al. Dec 1993