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US5374818: Identification means with integral memory device

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Filing Information

Inventor(s) James S. Bianco · David J. Horan ·
Assignee(s) Control Module Inc. ·
Attorney/Agent(s) John H. Crozier ·
Primary Examiner Cross; E. Rollins ·
Assistant Examiner Erick Solis ·
Application Number US7848242
Filing date 03/09/1992
Issue date 12/20/1994
Predicted expiration date 03/09/2012
U.S. Classifications 235/492  · 235/381  ·
International Classifications G06F 708  ·
Kind CodeA
International Classifications 235380;381;382;492 ·
16 Claims, No Drawings


Abstract

In one preferred embodiment, a memory device for insertion and retention in a hole defined in a planar identification card having upper and lower surfaces, the memory device comprising: electronic circuitry disposed in a cylindrical housing having upper and lower surfaces; the housing being held substantially within the hole after being snapped thereinto; and the housing having a total height substantially the same as the thickness of the card. In a further aspect of the invention, electronic circuitry in the housing is accessible by temporary attachment to an electronic terminal, the electronic circuitry being powered by a charged capacitor, the capacitor being adapted to be charged by the terminal with a charge sufficient to power the electronic circuitry for only a selected period of time. The capacitor may be charged over a communication line to the memory device. The memory may be disabled if a use limitation stored therein is exceeded.

Independent Claims | See all claims (16)

  1. 1. A memory device for insertion and retention in a hole defined in a planar identification card having upper and lower surfaces, said memory device comprising:(a) electronic circuitry disposed in a cylindrical housing having upper and lower surfaces, said housing having outwardly facing flanges formed around the outer peripheries of said upper and lower surfaces, forming therebetween an annular concave channel having a root portion, said flanges having a diameter slightly greater than the diameter of said hole and said root portion of said concave channel having diameter slightly less than said diameter of said hole;(b) said housing being held substantially within said hole after being snapped thereinto by the temporary elastic deformation of the periphery of said hole by said housing as said housing is inserted in said hole; and(c) said housing having a total height substantially the same as the thickness of said card.
  2. 4. A memory device for attachment to identification means, said memory device comprising: electronic circuitry therein accessible by temporary attachment to an electronic terminal, said electronic circuitry being powered by a charged capacitor, said capacitor being adapted to be charged by said terminal with a charge sufficient to power said electronic circuitry for only a selected period of time, said capacitor being charged over a data communication line to said memory device when said memory device is temporarily attached to said terminal.
  3. 9. A memory device for attachment to identification means, said memory device having stored therein data as to limitations of use of said identification means, electronic circuitry therein accessible by temporary attachment to an electronic terminal with a single connection over which data is communicated, said electronic circuitry including fusible means, and said electronic terminal being adapted to provide an electrical charge to said fusible means over said single connection to open said fusible means and disable said memory device when said electronic terminal determines that said limitations of use have been exceeded.
  4. 13. A method of restricting use of identification means, comprising the steps of:(a) providing electronic readable memory means on said identification means;(b) storing in said memory means limitations as to the use of said identification means;(c) temporarily attaching said identification means to a terminal such that data communication can take place between said memory means and said terminal over a single connection; and(d) disabling said memory means if said limitations have been exceeded, by providing a signal to said memory means over said single connection.

References Cited

U.S. Patent Documents

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Foreign Patent Documents

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Referenced By

Document NumberAssigneeInventorsIssue/Pub Date
US5969316 Cybermark LLC Dennis Keith Greer et al. Oct 1999
US5904590 Dallas Semiconductor Corporation Fekete; Nicholas M. G. May 1999
US5703395 Gay Freres S.A. Jean-Claude Berney Dec 1997
US5961356 Dallas Semiconductor Corporation Fekete; Nicholas M. G. Oct 1999
US7623624 Illumina, Inc. John A. Moon et al. Nov 2009
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US7843567 Illumina, Inc. John A. Moon et al. Nov 2010
US7604173 Illumina, Inc. Alan Kersey et al. Oct 2009
US7923260 Illumina, Inc. John A. Moon et al. Apr 2011
US8049893 Illumina, Inc. John A. Moon et al. Nov 2011
US8081792 Illumina, Inc. John A. Moon et al. Dec 2011
US8333325 Illumina, Inc. John A. Moon et al. Dec 2012
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