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US5777383: Semiconductor chip package with interconnect layers and routing and testing methods

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Filing Information

Inventor(s) Mark P. Stager · Abraham F. Yee · Gobi R. Padmanabhan ·
Assignee(s) LSI Logic Corporation ·
Attorney/Agent(s) D'Alessandro & Ritchie ·
Primary Examiner Tom Thomas ·
Assistant Examiner Alexander Oscar Williams ·
Application Number US8647344
Filing date 05/09/1996
Issue date 07/07/1998
Predicted expiration date 05/09/2016
U.S. Classifications 257/700  · 257/697  ·
International Classifications H01L 2353  ·
Kind CodeA
International Classifications 257700;697;698;691;693;703;737;738;206;211 ·
10 Claims, No Drawings


Abstract

A package for a semiconductor chip is provided which incorporates a plurality of levels of interconnect--conductive layers within the package which selectively direct signals to and from pins of the die and/or the pins of the package. A single general purpose chip may thus be fabricated in large quantities with the interconnect of the package used to define the specific purpose, functionality and pinout of the final device. Similarly, a standard package may be built to work with a large class of different chips and only the interconnect layers in the package need to be modified to allow the package to work with each different chip. In a second aspect of the invention, one or more layers of interconnect in the package may contain active electronic components which may be connected to nodes of the chip through the interconnect of the package and through the pins of the die. Accordingly, devices which are difficult or impossible to incorporate into a semiconductor die may be incorporated into a single package along with the die. In a third aspect of the invention, a method of integrated circuit design includes using a conventional CAD design tool software package to design not only the integrated circuit, but also variable circuit elements (such as interconnect and electronic components) embedded in the chip package. In a fourth aspect of the invention, a testing methodology for wafer die subcomponents is provided.

Independent Claims | See all claims (10)

  1. 1. A package for a semiconductor chip, said package comprising:a first layer having a first surface including a first level and a second level, said second level defining a chip receptacle area, said chip receptacle area located on said top surface;a plurality of conductive chip interface terminals disposed within said chip receptacle;a board interface including an array of a plurality of conductive board interface terminals, said array located on a second surface of the package, said second surface opposite from said first surface; anda plurality of interconnect layers disposed with the package, said layers including electrical connections to said chip interface terminals and electrical connections to said board interface terminals, wherein at least one of said interconnect layers within said plurality of interconnect layers contains an active component selected from the group consisting of diodes, zener diodes, transistors, FET's MOSFET's, LED's, and voltage regulators.
  2. 2. A method for designing an assembly formed FROM an integrated circuit wafer die and a package for the die, the package containing a plurality of interconnect layers, the method comprising the steps of:using a CAD design tool to design the electrical layout of the assembly;making the CAD design tool aware of the interconnect layers disposed within the die package;making the CAD design tool aware of a board interface including an array of a plurality of conductive board interface terminals, said array located on a second surface of the package, said second surface opposite from said first surface:having the CAD design tool prepare a design for the assembly including at least one electrical routing from the wafer die to the interconnect and back to the wafer die; andhaving the CAD design tool prepare a design for the assembly including at least one electrical routing from one of the interconnect layers to one of said conductive board interface terminals.
  3. 3. A method for designing an assembly including an integrated circuit wafer die and a die package, the die package including an electrical component, the method comprising the steps of:using a CAD design tool to design the electrical layout of the assembly;making the CAD design tool aware of the electrical component disposed within the die package;making the CAD design tool aware of a board interface including an array of a plurality of conductive board interface terminals, said array located on a second surface of the package, said second surface opposite from said first surface;having the CAD design tool prepare a design for the assembly including at least one electrical routing from the wafer die to the electrical component and back to the wafer die andhaving the CAD design tool prepare a design for the assembly including at least one electrical routine from one of the interconnect layers to one of said conductive board interface terminals.
  4. 4. A method for designing an assembly formed from an integrated circuit wafer die and a die package for encapsulating the die, the die package containing a plurality of interconnect layers and an electrical component, the method comprising the steps of:using a CAD design tool to design an electrical layout of the assembly;making the CAD design tool aware of the interconnect layers disposed within the die package;making the CAD design tool aware of the electrical component disposed within the die package;making the CAD design tool aware of a board interface including an array of a plurality of conductive board interface terminals, said array located on a second surface of the package, said second surface opposite from said first surface;having the CAD design tool prepare a design for the assembly including: at least one electrical routing from the wafer die to the interconnect and back to the wafer die, and at least one electrical routing from the wafer die to the electrical component and back to the wafer die; andhaving the CAD design tool prepare a design for the assembly including at least one electrical routing from one of the interconnect layers to one of said conductive board interface terminals.
  5. 5. A method for testing an uncut semiconductor wafer die disposed on a semiconductor wafer, the uncut die intended to be assembled to a package including at least a plurality of levels of interconnect, the method comprising the steps of:using a plurality of probes to interface a plurality of electrical signals to and from the die;interconnecting the probes together through probe interconnections to emulate the electrical function of the levels of interconnect that would be present if the die were mounted to its intended package; andtesting the die with signals designed to determine if it functions properly by passing test signals through said probe interconnections and through said probes.
  6. 6. An apparatus, comprising:a first layer having a top surface having a first level and a second level, said second level defining a chip receptacle area;a plurality of conductive chip interface terminals disposed on said second level within said chip receptacle area;a board interface including an array of a plurality of conductive board interface terminals, said array located on a bottom surface, said bottom surface opposite from said top surface; andat least one interconnect layer disposed between said top surface and said bottom surface, said layers including electrical connections to said chip interface terminals and electrical connections to said board interface terminals, wherein at least one of said interconnect layers within said plurality of interconnect layers contains an active component.
  7. 10.10. A method for designing an assembly formed from an integrated circuit wafer die and a die package for encapsulating the die, the method comprising the steps of:forming a plurality of interconnect layers and an electrical component to within the package;using a CAD design tool to design the electrical layout of the assembly;making the CAD design tool aware of the interconnect layers disposed within the die package;making the CAD design tool aware of the electrical component disposed within the die package;making the CAD design tool aware of a board interface having an array of a plurality of conductive board interface terminals, said array located on a second surface of the package, said second surface opposite from said first surface;having the CAD design tool prepare a design for the assembly including: at least one electrical routing from the wafer die to the package interconnect and back to the wafer die, and at least one electrical routing from the wafer die to the electrical component and back to the wafer die; andhaving the CAD design tool prepare a design for the assembly having at least one electrical routing from one of the package interconnect layers to one of said conductive board interface terminals.

References Cited

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Other Publications

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Referenced By

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