Fault tolerant extended processing complex for redundant nonvolatile file caching

Filing Information

• Patent Number: US5809543
• Application Number: US8745111
• Filing date: 11/07/1996
• Issue date: 09/15/1998
• Predicted expiration date: 12/23/2013

• U.S. Classifications: 711/162  · 711/120  ·
• International Classifications: G06F 1216 ·
• International Classifications: 395440;446;447;456-458;488;200.08;182.04;182.12;182.01;182.03;180;876 ·
• Related U.S. Application Data:
  CROSS REFERENCE TO RELATED PATENT APPLICATIONS
  This application is a continuation of application Ser. No. 08/173,459 filed on Dec. 23, 1993 and which is now abandoned. This application is related to the concurrently filed applications listed below, the disclosures of which are incorporated herein by reference. The identified applications are commonly assigned to Unisys Corporation, the assignee of the present invention:
  OUTBOARD FILE CACHE SYSTEM, Ser. No. 08/174,750 filed on Dec. 23,1993, invented by Thomas P. Cooper and Robert E. Swenson;
  DEDICATED POINT TO POINT FIBER OPTIC INTERFACE, Ser. No. 08/172,652, filed on Dec. 23, 1993, invented by Larry L. Byers, Donald Davies, Joseba M. Desubijana, Michael E. Mayer, Randall L. Piper, and Lloyd Thorsbakken, and which issued as U.S. Pat. No. 5,524,218 on Jun. 04, 1996;
  XPC HUB AND STREET ARCHITECTURE, Ser. No. 08/173,429, filed on Dec. 23, 1993, invented by Donald W. Mackenthun, Larry L. Byers, Gregory B. Wiedenman and Ferris T. Price (Deceased), and which issued as U.S. Pat. No. 5,495,589 on Feb. 27, 1996;
  ROUTING PRIORITIES WITHIN A HUB AND STREET ARCHITECTURE, Ser. No. 08/172,647, filed on Dec. 23, 1993, invented by Donald W. Mackenthun, and which issued as U.S. Pat. No. 5,450,578 on Sept. 12, 1995;
  MICRO SEQUENCER BUS CONTROLLER SYSTEM, Ser. No. 08/172,657, filed on Dec. 23, 1993, invented by Larry L. Byers, Joseba M. Desubijana, and Wayne Michaelson, and which issued as U.S. Pat. No. 5,535,405 on Jul. 09, 1996;
  FAULT TOLERANT CLOCK DISTRIBUTION SYSTEM, Ser. No. 08/172,661, filed on Dec. 23, 1993, invented by Larry L. Byers, Thomas T. Kubista, and Gregory B. Wiedenman, and which issued as U.S. Pat. No. 5,422,915 on Jun. 06, 1995;
  FOUR PORT RAM CELL, Ser. No. 08/173,379, filed Dec. 23, 1993, invented by Larry L. Byers, Duane Kurth, and Ashgar Malikt, and which issued as U.S. Pat. No. 5,434,818 on Jul. 18, 1995; and
  DATA COHERENCY PROTOCOL FOR MULTI-LEVEL CACHE HIGH PERFORMANCE MULTIPROCESSOR SYSTEM, Ser. No. 08/235,196, filed Apr. 29, 1994, invented by Kenichi Tsuchiya, Thomas Adelmeyer, Glen Kregness, Gary Lucas, Heidi Guck and Ferris Price, and which is a continuation of Ser. No. 07/762,276, filed Sept. 19, 1991, for which a File Wrapper Continuance Application was filed on Apr. 29, 1994 and which is now abandoned.
  This application is a continuation Ser. No. 08/173,459 filed on Dec. 23, 1993.
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Abstract

An outboard file cache extended processing complex for use with a host data processing system for providing closely coupled file caching capability is described. Data movers at the host provide the hardware interface to the outboard file cache, provide the formatting of file data and commands, and control the reading and writing of data from the extended processing complex. Host interface adapters receive file access commands sent from the data movers and provide cache access control. Directly coupled fiber optic links couple each of the data movers to the associated one of the host interface adapters and from the nonvolatile memory. A nonvolatile memory to store redundant copies of the cached file data is described. A system interface including bidirectional bus structures and index processors that control the routing of data signals, provides control of storage and retrieval of file cache data derived from host interface adapters and from the nonvolatile memory. Multiple power domains are described together with independent clock distribution within each power domain. The independent clock distribution sources are synchronized with each other. A system for fault tolerant redundant storage of file cache data redundantly in at least two portions of the nonvolatile file cache storage is described.

Independent Claims | See all claims (45)

1. 1. For use with a host data processing system for processing and modifying data files and having an instruction processor, a storage controller, a file mass storage device for storing the data files, main operational memory coupled to the storage controller, a data mover system to control the reading and writing of the data files to and from the host data processing system and being coupled to the instruction processor and to the main operational memory, and a transmission link coupled to the data mover, an outboard file cache external processing complex comprising:a bidirectional bus structure;a host interface adapter having host coupling terminals to be coupled to the transmission link to receive the data files and command signals from the host data processor systems and to transmit the data files and said command signals to the host data processing system, and having bus coupling terminals coupled to said bidirectional bus structure;an index processor coupled to said bidirectional bus structure to control transmission of the data files and said command signals on said bidirectional bus structure;a file-relative addressable nonvolatile storage system adapted to selectively redundantly cache the data files received from the host data processing system so that multiple copies of each data file are cached substantially simultaneously, said addressable nonvolatile storage system further adapted to selectively read the data files; anda storage interface control circuit coupled to said addressable nonvolatile storage system and to said bidirectional bus structure to receive said command signals and in response thereto, to control selectively redundantly storing the data files in said file-relative addressable nonvolatile storage system and to further control selectively reading the data files from said file-relative addressable nonvolatile storage system,whereby file caching and control is closely coupled to the host data processing system and is accomplished in parallel to file data processing and related control functions performed by the host data processing system.
2. 7. For use with a host data processing system for processing file data signals described in data files, an outboard file cache system comprising:a data mover circuit having input terminals to be coupled to the host data processing system, said data mover circuit having first link terminals;a host interface adapter circuit having second link terminals;a bidirectional link coupled between said first link terminals and second link terminals;system interface circuits coupled to said host interface adapter circuit and including routing control circuits, bidirectional busses, storage interface control circuits, and storage access terminals; anda file addressable redundant nonvolatile storage system coupled to said storage access terminals to selectively redundantly cache selected ones of the data files processed by the host data processing system.
3. 15. For use in a host data processing system for processing file data signals and having at least one instruction processor, a storage controller, a file mass storage device for storing file data signals that compose data files, main operational memory for use by the instruction processor, data mover circuits to control reading and writing of the file data signals to and from the host data processing system, each of the data mover circuits are coupled to the instruction processor and to the main operational memory, and a separate transmission link coupled to each of the data mover circuits, an outboard file cache external processing complex comprising:first and second bidirectional bus structures;first and second host interface adapter circuits, each having host coupling terminals to be coupled to an associated one of the transmission links to receive the data files and command signals from the associated data mover circuit in the host data processing system and to transmit the data files and said command signals to the associated data mover circuit in the host data processing system, and having bus coupling terminals wherein said first host interface adapter circuit is coupled to said first bidirectional bus structure and said second host interface adapter circuit is coupled to said second bidirectional bus structure;a first index processor couple to said first bidirectional bus structure and a second index processor coupled to said second bidirectional bus structure, each of said first and second index processors to control transmission of the data files and said command signals on the associated one of said first and second bidirectional bus structures;first and second addressable nonvolatile storage devices, each adapted to selectively and substantially simultaneously cache multiple copies of the data files and to selectively read the data files;first and second storage interface control circuits, said first storage interface control circuit coupled to said first bidirectional bus structure and said second storage interface control circuit coupled to said second bidirectional bus structure, and said first and second storage interface control circuits each coupled to said addressable nonvolatile storage devices, wherein said first and second storage interface control circuits control said cache and said read operations of the data files in response to said command signals thereby storing duplicate copies of the data files in said first and second addressable nonvolatile storage devices.
4. 23. For use with a host data processing system for processing and modifying data files, each data file being referenced by a file identifier and file offsets, an outboard file cache system comprising:redundant nonvolatile file cache storage means for receiving copies of selected ones of the data files from the host data processing system and for redundantly storing duplicate cached copies of said selected ones of the data files, each of said selected ones of the data files being stored substantially simultaneously with the associated said duplicate cached copy;file cache storage interface means coupled to said redundant nonvolatile cache storage means for controlling caching and retrieval operations for said duplicate cached copies of said selected ones of the data files according to file identifiers and file offsets associated with said selected ones of the data files;index processor means coupled to said file cache storage interface means for controlling transmission of said selected ones of the data files and command signals to and from said redundant nonvolatile file cache storage means;host interface adapter means coupled to said file cache storage interface means for formatting said selected ones of the data files received from and to be sent to the host data processing system and for providing said selected ones of the data files to be cached by said redundant nonvolatile file cache storage means;bidirectional bus means coupled to said file cache storage interface means, said index processor means, and said host interface adapter means for transmitting said selected ones of the data files;bidirectional link means coupled to said host interface adapter means for transmitting said selected ones of the data files and said command signals; anddata mover means coupled to said link means for formatting and controlling said selected ones of the data files at the host data processing system.
5. 32. For use with a data processing system having n hosts for processing file data signals which compose data files, where n is an integer greater than one, an outboard file cache system comprising:2n data mover circuits, each of said 2n data mover circuits having input terminals to be coupled in pairs to associated ones of the n hosts and each of said 2n data mover circuits having first link terminals;2n host interface adapter circuits, each of said 2n host adapter circuits having second link terminals;2n bidirectional links, each of said 2n bidirectional links coupled between associated ones of said first link terminals and said second link terminals;2n system interface circuits, each of said 2n system interface circuits coupled to adjacent ones of said 2n system interface circuits and coupled to an associated one of said 2n host interface adapter circuits, each of said 2n system interface circuits including routing control circuits, bidirectional busses, storage interface control circuits, and storage access terminals, and2n addressable nonvolatile storage devices arranged in pairs, each of said pairs of said 2n addressable nonvolatile storage devices coupled to said storage access terminals of associated pairs of said 2n system interface circuits to selectively redundantly cache file data signals of selected ones of the data files.
6. 42. For use with a host data processing system for processing data files addressed using file identifiers and file offsets, a fault tolerant file cache system comprising:redundant nonvolatile file cache storage means for receiving data files from the host data processing system and for redundantly storing duplicate cached copies of the data files substantially simultaneously according to the file identifiers and file offsets;host interface adapter means for formatting the data files received from and to be sent to the host data processing system and for providing the data files to be cached; andcache control means coupled to said redundant nonvolatile file cache means and to said host interface adapter means for controlling the redundant storage and retrieval of the data files.