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US5985755: Processing for polishing dissimilar conductive layers in a semiconductor device

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Filing Information

Inventor(s) Rajeev Bajaj · Janos Farkas · Sung C. Kim · Jaime Saravia ·
Assignee(s) None listed in document.
Primary Examiner John F. Niebling ·
Assistant Examiner David A. Zarneke ·
Application Number US8822025
Filing date 03/24/1997
Issue date 11/16/1999
Predicted expiration date 03/24/2017
U.S. Classifications 438/645  · 438/628  ·
International Classifications H01L 214763  ·
Kind CodeA
International Classifications 438628;629;644;652;654;626;633;645;689-693 ·
Related U.S. Application DataCROSS-REFERENCE TO RELATED APPLICATION
The present invention relates to the following commonly assigned, copending applications:
1) "Process for Polishing A Semiconductor Device Substrate," by Kim et al., Ser. No. 08/780,113, filed Dec. 26, 1996; and
2) "Process for Forming A Semiconductor Device," by Nagabushnam et al., Ser. No. 08/783,975, filed Jan. 15, 1997; and
3) "Slurry for Chemically-Mechanically Polishing a Layer and Method of Use," by Farkas et al., Ser. No. 08/684,782, filed Jul. 22, 1996.
22 Claims, No Drawings


Abstract

A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different source containers (111 and 112), wherein the first slurry is dispensed until the tungsten is removed and then the slurry dispense is switched to the second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Independent Claims | See all claims (22)

  1. 1. A process for forming a semiconductor device comprising:providing a substrate having:a semiconductor material;a patterned insulating layer overlying the semiconductor material, wherein the patterned insulating layer includes an opening;a first conductive layer including a first material lying over the patterned insulating layer and within the opening;a second conductive layer including a second material that is different from the first material overlying the first conductive layer;polishing the second conductive layer with a first polishing fluid including a first oxidizing component to expose a portion of the first conductive layer; andpolishing the first conductive layer with a second polishing fluid including a second oxidizing component that is different from the first oxidizing component to expose a portion of the patterned insulating layer.
  2. 14. A process of forming a semiconductor device comprising:providing a semiconductor substrate having a conductive member;depositing an insulating layer over the semiconductor substrate, including over the conductive member;forming a via opening in the insulating layer which exposes the conductive member;depositing a first conductive layer over the insulating layer, including into the via opening;depositing a second conductive layer, different in composition from the first conductive layer, on the first conductive layer;providing a polisher having a polishing pad;polishing the second conductive layer using a first polishing fluid dispensed onto the polishing pad at least until the first conductive layer is exposed; andpolishing the first conductive layer using a second polishing fluid, wherein an oxidizing component of the second polishing fluid is different than an oxidizing component of the first polishing fluid.

References Cited

U.S. Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
US4448634 Wacker-Chemitronic Gesellschaft fur Elektronik-Grundstoffe mbH Lampert May 1984
US5209816 Micron Technology, Inc. Yu et al. May 1993
US5352277 E. I. Du Pont de Nemours & Company Sasaki Oct 1994
US5516346 Intel Corporation Cadien et al. May 1996
US5676587 International Business Machines Corporation Landers et al. Oct 1997
US5700383 Intel Corporation Feller et al. Dec 1997
US5756398 Rodel, Inc. Wang et al. May 1998
US5858813 Cabot Corporation Scherber et al. May 1996

Foreign Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
JP1133218May 1989
JP2285518Nov 1990

Other Publications

Brown et al., "Electrochemical and in situ atomic force microscopy and scanning tunneling microscopy investigations of titanium in oxalic acid solution"; J. Vac. Technl. vol. 10 No. 5 Sep./Oct. 1992, pp. 3001-3006.

Referenced By

Patent Family

Document NumberAssigneeInventorsIssue/Pub Date
CN1194453 MOTOROLA CORP BAGAY RAGIF et al. Sep 1998
EP0871214 MOTOROLA, INC. Rajeev Bajaj et al. Oct 1998
US5985755 Rajeev Bajaj et al. Nov 1999
TW379377 MOTOROLA INC BAJAJ RAJEEV et al. Jan 2000
US6204169 Motorola Inc. Rajeev Bajaj et al. Mar 2001
SG79962 MOTOROLA INC RAJEEV BAJAJ et al. Apr 2001
DE69839136 FREESCALE SEMICONDUCTOR INC BAJAJ RAJEEV et al. Apr 2008