Method and apparatus for performing partial unscan and near full scan within design for test applications
Filing Information
- Patent Number: US6067650
- Application Number: US8985614
- Filing date: 12/05/1997
- Issue date: 05/23/2000
- Predicted expiration date: 05/17/2016
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analyzing 100 million+ documents to uncover your network...- U.S. Classifications: 714/726 · 714/724 ·
- International Classifications: G01R 3128 ·
- International Classifications: 714726;724 ·
- Related U.S. Application Data:
This is a continuation of copending application Ser. No. 08/649,788 filed on May 17, 1996, now U.S. Pat. No. 5,696,771 which is hereby incorporated by reference to this specification which designated the U.S.
Abstract
A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability while still maintaining specified optimization (e.g., area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are scan replaced) that does not meet determined optimization constraints. The novel subtractive system unscans selected cells until the area and/or timing constraints are met. A flag indicates whether nor not timing is considered. Selection for unscanning is based on a testability cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned first. The additive process receives an unscanned netlist (original design) and scan replaces cells, using the TCL ranked list until optimization (e.g., area and/or timing) constraints of the design are violated. A flag indicates whether nor not timing is considered. The additive system iterates through the TCL list with the cells offering the most contribution for testability scan replaced first.References Cited
U.S. Patent Documents
| Document Number | Assignees | Inventors | Issue/Pub Date |
|---|---|---|---|
| US5396435 | VLSI Technology, Inc. | Ginetti | Mar 1995 |
| US5459673 | Ross Technology, Inc. | Carimean et al. | Oct 1995 |
| US5463563 | LSI Logic Corporation | Bair et al. | Oct 1995 |
| US5502661 | Siemens Aktiengesellschaft | Glunz | Mar 1996 |
| US5544066 | LSI Logic Corporation | Rostoker et al. | Aug 1996 |
| US5696771 | Synopsys, Inc. | Beausang et al. | Dec 1997 |
Referenced By
Patent Family
| Document Number | Assignee | Inventors | Issue/Pub Date |
|---|---|---|---|
| US5696771 | Synopsys, Inc. | James Beausang et al. | Dec 1997 |
| US6067650 | Synopsys, Inc. | James Beausang et al. | May 2000 |
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Independent Claims | See all claims (16)
- 1. In a computer implemented synthesis system, a subtractive method of generating a netlist containing scan replaced sequential cells and satisfying determined optimization constraints, said method comprising the computer implemented steps of:a) accessing an input netlist containing scan replaced sequential cells;b) determining a set of critical paths within said input netlist;c) selecting a selected critical path of said set of critical paths and identifying a first sequential cell and a second sequential cell located on either end of said selected critical path;d) provided said first sequential cell and said second sequential cell are both scan replaced, determining which sequential cell of said first and second sequential cells contributes least to testability;e) within said input netlist, unscanning said sequential cell of said selected critical path that contributes least to testability; andf) repeating steps b)-e) while there are critical paths in said set of critical paths that have scan replaced cells and there are no worse critical paths that have no scan replaced cells.
- 6. In a computer system having a processor coupled to a bus and a memory coupled to said bus, a computer implemented subtractive method of generating a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said method comprising the computer implemented steps of:a) provided a timing critical selection is asserted, unscanning scan replaced sequential cells that violate said timing constraints, said step a) comprising the steps of:a1) accessing a fully scan replaced input netlist;a2) performing a timing analysis on said input netlist to determine a set of critical paths located therein;a3) selecting a particular critical path of said set of critical paths and identifying a first sequential cell and a second sequential cell located on either end of said particular critical path;a4) provided said first and second sequential cells are both scan replaced, determining which contributes least to testability;a5) within said input netlist, unscanning said sequential cell of said particular critical path that contributes least to testability; anda6) repeating steps a2)-a5) while critical paths having scan replaced cells exist within said set of critical paths and no worse critical paths exist that have no scan replaced cells;b) provided said area constraints are violated by said input netlist, selecting a particular scan replaced cell having a low contribution to testability and unscanning said particular scan replaced cell; andc) repeating step b) until all cells are unscanned or until said area constraints are satisfied.
- 9. In a computer system, an additive method of generating a netlist having scan replaced sequential cells and satisfying determined timing constraints, said method comprising the computer implemented steps of:a) accessing an unscanned input netlist including unscanned sequential cells and having an indication of its worst critical path;b) selecting a particular unscanned sequential cell characterized in that it has high contributions to testability;c) scanning said particular unscanned sequential cell within said input netlist provided said step of scanning does not worsen timing characteristics of said input netlist;d) selecting a next particular unscanned sequential cell; ande) repeating steps c)-d) for each unscanned sequential cell.
- 13. In a computer system, an additive method of generating a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said method comprising the computer implemented steps of:a) accessing an unscanned input netlist including unscanned sequential cells and having an indication of its worst critical path;b) selecting a particular unscanned sequential cell characterized in that it has high contributions to testability;c) scanning said particular unscanned sequential cell, provided said step of scanning does not worsen timing characteristics or violate timing constraints of said input netlist, wherein said step c) further comprises the steps of:c1) copying said input netlist to generate an input netlist copy;c2) scanning said particular unscanned sequential cell within said input netlist copy;c4) determining the worst critical path of said copy of said input netlist;c5) summing the areas of each logic and routing element of said input netlist copy to determine an area of said input netlist copy; andc6) scanning said particular unscanned sequential cell within said input netlist provided said worst critical path of said input netlist copy is not worse than said worse critical path of said input netlist and provided said area of said input netlist copy does not violate said area constraints;d) selecting a next particular unscanned sequential cell; ande) repeating steps c)-d) for each unscanned sequential cell.
- 16.16. A computer system comprising:a processor coupled to a bus; anda computer readable memory unit coupled to said bus, said memory unit having a program stored therein causing said computer system to generate a netlist having scan replaced sequential cells and satisfying determined timing and area constraints, said program causing said processor to perform the steps of:a) accessing an unscanned input netlist including unscanned sequential cells and having an indication of its worst critical path;b) selecting a particular unscanned sequential cell characterized in that it has high contributions to testability;c) scanning said particular unscanned sequential cell, provided said step of scanning does not worsen timing characteristics or violate timing constraints of said input netlist, wherein said step c) further comprises the steps of:c1) copying said input netlist to generate an input netlist copy;c2) scanning said particular unscanned sequential cell within said input netlist copy;c4) determining the worst critical path of said copy of said input netlist;c5) summing the areas of each logic and routing element of said input netlist copy to determine an area of said input netlist copy; andc6) scanning said particular unscanned sequential cell within said input netlist provided said worst critical path of said input netlist copy is not worse than said worse critical path of said input netlist and provided said area of said input netlist copy does not violate said area constraints;d) selecting a next particular unscanned sequential cell; ande) repeating steps c)-d) for each unscanned sequential cell.
