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US6690055: Devices containing platinum-rhodium layers and methods

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Filing Information

Inventor(s) Stefan Uhlenbrock · Eugene P. Marsh ·
Assignee(s) Micron Technology, Inc. ·
Attorney/Agent(s) Mueting, Raasch & Gebhardt, P.A. ·
Primary Examiner George Eckert ·
Assistant Examiner N. Drew Richards ·
Application Number US9651699
Filing date 08/30/2000
Issue date 02/10/2004
Predicted expiration date 03/02/2019
Patent term adjustment 188
U.S. Classifications 257/310  · 257/768  · 257/532  · 257/769  · 257/296  ·
International Classifications --
Kind CodeB1
International Classifications 257310 · 257296 · 257532 · 257751 · 257768 · 257769 ·
Related U.S. Application DataCROSS-REFERENCE TO RELATED APPLICATION
This is a division of application Ser. No. 09/146,556, filed Sep. 3, 1998, (U.S. Pat. No. 6,271,131), which is a continuation-in-part of application Ser. No. 09/140,921, filed Aug. 26, 1998, (abandoned) both of which are incorporated herein by references.
20 Claims, 16 Drawings


Abstract

A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Independent Claims | See all claims (20)

  1. 1. A capacitor comprising a first electrode, a dielectric layer, and a second electrode, wherein at least one of said first or second electrodes consists of a single layer comprising a CVD platinum-rhodium alloy.
  2. 5. A capacitor comprising a dielectric layer, a first electrode, a second electrode, and a conductive barrier layer comprising a CVD platinum-rhodium alloy adjacent said first electrode, wherein said first electrode does not comprise a platinum-rhodium alloy.
  3. 11. An integrated circuit comprising a capacitor, said capacitor comprising a first electrode, a dielectric layer, and a second electrode, wherein at least one of said first or second electrodes consists of a single layer comprising a CVD platinum-rhodiumn alloy.
  4. 15. An integrated circuit comprising a capacitor, said capacitor comprising a dielectric layer, a first electrode, a second electrode, and a conductive barrier layer comprising a CVD platinum-rhodium alloy adjacent said first electrode, wherein said first electrode does not comprise a platinum-rhodium alloy.
  5. 19. A memory cell comprising: a transistor; and a capacitor comprising a first electrode, a second electrode, and a diffusion barrier layer comprising a CVD platinum-rhodium alloy adjacent said first electrode, wherein said first electrode does not comprise a platinum-rhodium alloy.

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