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US6900128: Activation of oxides for electroless plating

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Filing Information

Inventor(s) Nishant Sinha ·
Assignee(s) Micron Technology, Inc. ·
Attorney/Agent(s) Dinsmore & Shohl LLP ·
Primary Examiner Asok Kumar Sarkar ·
Application Number US10929853
Filing date 08/30/2004
Issue date 05/31/2005
Prior Publication Data
Predicted expiration date 08/19/2022
U.S. Classifications 438/678  · 438/686  · 438/680  · 438/754  · 438/677  ·
International Classifications --
Kind CodeB2
International Classifications 438618 · 438633 · 438656 · 438677 · 438678 · 438680 · 438686 · 438745 · 438754 · 438785 · 427601 · 205 80 · 205104 · 205322 ·
Related U.S. Application DataCROSS REFERENCE TO RELATED APPLICATIONS
This application is a division of U.S. patent application Ser. No. 10/223,315, filed Aug. 19, 2002.
33 Claims, 5 Drawings


Abstract

The present invention provides approaches for electroless deposition of conductive materials onto the surface of oxide-based materials, including nonconductive metal oxides, in a manner that does not require intervening conductive pastes, nucleation layers, or additional seed or activation layers formed over the surface of the oxide-based layer. According to one embodiment of the present invention, a layer of a titanium-based material is formed over an oxide-based surface. The layer of titanium-based material is subsequently removed from the surface of the oxide-based layer in a manner such that the surface of the oxide-based layer is activated for electroless deposition. A metal or metal alloy is then plated over the oxide-based surface using electroless plating techniques.

Independent Claims | See all claims (33)

  1. 1. A method of fabricating a semiconductor device comprising: forming an oxide-based layer over a semiconductor substrate; forming at least one opening in said oxide-based layer; forming a titanium-based layer over said oxide-based layer such that said titanium-based layer overlies at least a portion of said at least one opening; removing said titanium-based layer from said oxide-based layer; depositing a first conductive layer over said oxide-based layer using electroless plating; and, depositing a second conductive layer over said first conductive layer.
  2. 13. A method of filling a via comprising: etching an opening in an oxide-based layer of a semiconductor device; filling at least said opening with a titanium-based material; removing said titanium-based material from said opening; electrolessly plating directly to said oxide-based layer at least within said opening with a first conductive material; and, filling said opening with a second conductive material.
  3. 14. A method of filling a via comprising: etching an opening in an oxide-based layer of a semiconductor device; depositing a titanium-based material onto said oxide-based layer such that said titanium-based material at least partially fills said opening; etching said titanium-based material from said opening; electrolessly plating directly to said oxide-based layer at least within said opening with a first conductive material; and, filling said opening with a second conductive material.
  4. 15. A method of filling a via comprising: etching an opening in an oxide-based layer of a semiconductor device; depositing a titanium-based material onto said oxide-based layer such that said titanium-based material at least partially fills said opening, said titanium-based material deposited using a chemical vapor deposition process at a temperature of at least 550 degrees Celsius; wet chemical etching said titanium-based material from said opening; electrolessly plating directly to said oxide-based layer at least within said opening with a first conductive material; and, filling said opening with a second conductive material.
  5. 20. A semiconductor device fabricated according to the process comprising: forming an oxide-based layer over a semiconductor substrate; forming at least one opening in said oxide-based layer; depositing a titanium-based layer over said oxide-based layer such that said titanium-based layer overlies at least a portion of said at least one opening; removing said titanium-based layer from said oxide-based layer; depositing a first conductive layer over said oxide-based layer using electroless plating; and, depositing a second conductive layer over said first conductive layer.
  6. 21. A method of forming a capacitor comprising: forming a first dielectric layer over a base substrate; forming a capacitor container in said first dielectric layer; forming a titanium-based layer over at least a portion of said first dielectric layer and within said capacitor container; removing said titanium-based layer from said first dielectric layer; performing electroless plating of a first conductive layer over said first dielectric layer and within said capacitor container; forming a second conductive layer over said first conductive layer at least within said capacitor container; depositing a second dielectric layer within said capacitor container and over said second conductive layer; and, depositing a third conductive layer over said second dielectric layer.

References Cited

U.S. Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
US5169680* Intel Corporation Ting et al. Dec 1992
US5824599* Cornell Research Foundation, Inc. Schacham-Diamand et al. Oct 1998
US5891513 Cornell Research Foundation Dubin et al. Apr 1999
US6054172 Micron Technology, Inc. Robinson et al. Apr 2000
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* cited by examiner

Other Publications

Tetsuya Osaka, Nao Takano, Tetsuya Kurokawa, Tomomi Kaneko, and Kazuyoshi Ueno; Electroless Nickel Ternary Alloy Deposition on SiO2 for Application to Diffusion Barrier Layer in Copper Interconnect Technology; Journal of The Electrochemical Society; 2002; C573-C578; The Electrochemical Society, Inc.; Japan.

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