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US7015500: Memory device utilizing carbon nanotubes

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Filing Information

Inventor(s) Won-bong Choi · In-kyeong Yoo · Jae-uk Chu ·
Assignee(s) Samsung Electronics Co., Ltd. ·
Attorney/Agent(s) Lee & Morse, P.C. ·
Primary Examiner Minhloan Tran ·
Assistant Examiner Thomas L. Dickey ·
Application Number US10361024
Filing date 02/10/2003
Issue date 03/21/2006
Prior Publication Data
Predicted expiration date 02/10/2023
U.S. Classifications 257/40  · 257/324  · 257/321  · 257/288  ·
International Classifications H01B708  · H01L3524  ·
Kind CodeB2
Foreign Priority KR20027709 - 02/09/2002 · KR1020020071398 - 11/16/2002 ·
18 Claims, 18 Drawings


Abstract

A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Independent Claims | See all claims (18)

  1. 1. A carbon nanotube memory device, comprising: a substrate; a source electrode and a drain electrode arranged with a predetermined interval between them on the substrate and subjected to a voltage; a carbon nanotube connecting the source electrode to the drain electrode and serving as a channel for charges; a memory cell, located over the carbon nanotube, that stores charges from the carbon nanotube, the memory cell including: a first insulating film formed in contact with the upper surface of the carbon nanotube; a charge storage film, deposited on the first insulating film, that stores charges; and a second insulating film formed on the charge storage film and contacting the gate electrode, wherein a thickness of the second insulating film is approximately double a thickness of the charge storage film; and a gate electrode, formed in contact with the upper surface of the memory cell, for controlling the amount of charge flowing from the carbon nanotube into the memory cell.
  2. 12. A carbon nanotube memory device, comprising: a substrate; a source electrode and a drain electrode arranged with a predetermined interval between them on the substrate and subjected to a voltage; a carbon nanotube connecting the source electrode to the drain electrode and serving as a channel for charges; a memory cell, located over the carbon nanotube, that stores charges from the carbon nanotube, the memory cell including: a third insulating film formed in contact with the lower surface of a gate electrode; and a porous film positioned below the third insulating film and formed in direct contact with the carbon nanotube, the porous film having a plurality of nanodots filled with a charge storage material, the charge storage material being in contact with the third insulating film; and the gate electrode, formed in contact with the upper surface of the memory cell, for controlling the amount of charge flowing from the carbon nanotube into the memory cell.
  3. 17. A carbon nanotube memory device, comprising: a substrate; a source electrode and a drain electrode arranged with a predetermined interval between them on the substrate and subjected to a voltage; a carbon nanotube connecting the source electrode to the drain electrode and serving as a channel for charges; a memory cell, located over the carbon nanotube, that stores charges from the carbon nanotube, the memory cell including: a third insulating film formed in contact with the lower surface of a gate electrode; and a porous film positioned below the third insulating film and formed in contact with the carbon nanotube, the porous film having a plurality of nanodots filled with a charge storage material; and the gate electrode, formed in contact with the upper surface of the memory cell, for controlling the amount of charge flowing from the carbon nanotube into the memory cell, wherein the thickness of the third insulating film is approximately double the thickness of the porous film.
  4. 18. A carbon nanotube memory device, comprising: a substrate; a source electrode and a drain electrode arranged with a predetermined interval between them on the substrate and subjected to a voltage; a carbon nanotube connecting the source electrode to the drain electrode and serving as a channel for charges; a memory cell, located over the carbon nanotube, that stores charges from the carbon nanotube, the memory cell including: a third insulating film formed in contact with the lower surface of a gate electrode; and a porous film positioned below the third insulating film and formed in contact with the carbon nanotube, the porous film having a plurality of nanodots filled with a charge storage material; and the gate electrode, formed in contact with the upper surface of the memory cell, for controlling the amount of charge flowing from the carbon nanotube into the memory cell, wherein the porous film is made of aluminum oxide.

References Cited

U.S. Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
US6515339* LG Electronics Inc. Shin et al. Feb 2003
US20020153160* Hofmann et al. Oct 2002

Foreign Patent Documents

Document NumberAssigneesInventorsIssue/Pub Date
EP1091418Saifun Semiconductors LtdApr 2001
* cited by examiner

Other Publications

Tans, S. et al, “Room-temperature transistor based on a single carbon . . . ”, Nature, 393:49-52 (May 1998).
Tans, S. et al, “Potential modulations along carbon nanotubes”, Nature, 404:834 (Apr. 2000).
Choi et al, “Carbon-nanotube-based nonvolatile . . . ”, Applied Physics Letters, 82(2):275-277 (Jan. 2003).

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