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US7132371: Dopant barrier for doped glass in memory devices

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Filing Information

Inventor(s) Kunal R. Parekh · Gurtej Singh Sandhu ·
Assignee(s) Micron Technology, Inc ·
Attorney/Agent(s) Schwegman, Lundberg, Woessner & Kluth, P.A. ·
Primary Examiner Scott B. Geyer ·
Application Number US10931591
Filing date 08/31/2004
Issue date 11/07/2006
Prior Publication Data
Predicted expiration date 08/29/2022
U.S. Classifications 438/763  ·
International Classifications H01L2131  ·
Kind CodeB2
Related U.S. Application DataThis application is a Divisional of U.S. application Ser. No. 10/233,279, filed Aug. 29, 2002, now U.S. Pat. No. 6,833,575, which is incorporated herein by reference.
48 Claims, 16 Drawings


Abstract

A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

Independent Claims | See all claims (48)

  1. 1. A method comprising: forming a surface structure on a substrate; forming a diffusion barrier including an alumina layer on the surface structure; and forming a doped glass layer over the alumina layer, wherein forming the diffusion barrier further includes forming a first insulating layer between the doped glass layer and the surface structure and the substrate, wherein the first insulating layer is formed before the alumina is formed, wherein forming the diffusion barrier further includes forming a second insulating layer over the alumina layer, and wherein the alumina layer is sandwiched between the first and second insulating layers.
  2. 10. A method of forming a memory device, the method comprising: forming a plurality of diffusion regions in a substrate, the diffusion regions being separated by a plurality of channel regions, each of the channel regions being located between two adjacent diffusion regions; forming a plurality of gate structures over the substrate, each of the gate structures being formed over a selected channel region, wherein the diffusion regions and the gate structures form a plurality of transistors, and wherein one of the diffusion regions is shared by two transistors of the plurality of transistors; forming a diffusion barrier including forming an alumina layer on the gate structures and the substrate such that the alumina layer is conforming to each of the gate structures; and forming a doped glass layer over the diffusion barrier.
  3. 23. A method comprising: forming a word line of a memory cell, the word line is formed over a substrate; forming an alumina layer over the word line, wherein the alumina layer has a thickness in a range of about 20 Angstroms to about 200 Angstroms; forming a doped glass layer over the alumina layer; forming a first insulating layer between the word line and the doped glass layer; and forming a second insulating layer, wherein the first insulating layer is formed before the alumina layer is formed, and wherein the second insulating layer is formed after the alumina is formed such that the alumina layer is sandwiched between the first insulating layer and the second isulating layer.
  4. 30. A method comprising: forming a first diffusion region and a second diffusion in a substrate, the first and second diffusion regions being separated by only a channel region in the substrate; forming a gate structure over the substrate and opposing the channel region; forming a diffusion barrier including forming an alumina layer, the diffusion barrier conforming to the gate structure, wherein the diffusion layer is formed such that at least a portion of the diffusion layer directly contacts one of the first and second diffusion regions; forming a doped glass layer over the diffusion barrier; forming a first contact through the doped glass layer and directly contacting the first doped region; and forming a second contact through the doped glass layer and directly contacting the second doped region.
  5. 42. A method comprising: forming in a substrate a first diffusion region, a second diffusion region, and a third diffusion region; forming over the substrate a first gate structure and a second gate structure, wherein the first and second diffusion regions and the first gate structure form a first transistor, and wherein the second and third diffusion regions and the second gate structure form a second transistor, and wherein the second diffusion region is shared by the first and second transistors; forming a diffusion barrier including forming an alumina layer, such that the alumina layer is conforming to the first and second gate structures; forming a doped glass layer over the diffusion barrier; forming a first contact through the doped glass layer and coupled to the first doped region; forming a second contact through the doped glass layer and coupled to the second doped region; and forming a third contact through the doped glass layer and coupled to the third doped region.

Referenced By

Document NumberAssigneeInventorsIssue/Pub Date
US7411255 Micron Technology, Inc. Kunal R. Parekh et al. Aug 2008
US7566667 Samsung Electronics Co., Ltd. Eung-Joon Lee et al. Jul 2009