Browsing U.S. Classifications

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  • 710: ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT
    • 710/240: ACCESS ARBITRATING
      • 710/241: Centralized arbitrating
      • 710/242: Decentralized arbitrating
      • 710/243: Hierarchical or multilevel arbitrating
      • 710/244: Access prioritizing

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Method and apparatus for transferring data on a split bus in a data processing system U.S. Patent US6240479 | Filed: 07/31/1998 | Issued: 05/29/2001 Assignee(s): Motorola, Inc. | Inventor(s): Michael Dean Snyder + 3 | Agent(s): James L. Clingan, Jr. | Examiner(s): Ario Etienne A bus protocol for a split bus (50, 60) where each device (10, 20, 30) coupled to the bus has an age-based queue (12, 24, 34) of pending transactions. Queues are updated as transactions are execute...

Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch U.S. Patent US6185221 | Filed: 11/09/1998 | Issued: 02/06/2001 Assignee(s): Cabletron Systems, Inc. | Inventor(s): Gnes Aybay | Agent(s): Law Offices of Mark A. Wilson + 1 | Examiner(s): Chi H. Pham An input-buffered multipoint switch having input channels and output channels includes multilevel request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multilevel req...

Pipelined arbitration system and method U.S. Patent US6167478 | Filed: 10/05/1998 | Issued: 12/26/2000 Assignee(s): Infineon Technologies North America Corp. | Inventor(s): Tommaso Bacigalupo | Examiner(s): Glenn A. Auve An access control system (10) for controlling access to a shared resource among a plurality of service requestors is described. When a service requestor seeks access to the shared resource, it gene...

Elimination of traps and atomics in thread synchronization U.S. Patent US6230230 | Filed: 12/03/1998 | Issued: 05/08/2001 Assignee(s): Sun Microsystems, Inc. | Inventor(s): William N. Joy + 2 | Agent(s): Skjerven Morrill MacPherson LLP + 1 | Examiner(s): Ario Etienne Elimination of traps and atomics in thread synchronization is provided. In one embodiment, a processor includes a lock cache. The lock cache holds a value that corresponds to or identifies a comput...

Pci bus system wherein target latency information are transmitted along with a retry request U.S. Patent US6282598 | Filed: 04/17/1998 | Issued: 08/28/2001 Assignee(s): NEC Corporation | Inventor(s): Masao Manabe | Agent(s): Ostrolenk, Faber, Gerb & Soffen, LLP | Examiner(s): Ario Etienne In a PCI bus system comprising an initiator and a target, wherein data is transferred from the target via a PCI bus in response to access from the initiator, a time intercal period required from ac...

Method for gradual deployment of user-access security within a data processing system U.S. Patent US5991879 | Filed: 10/23/1997 | Issued: 11/23/1999 Assignee(s): Bull HN Information Systems Inc. | Inventor(s): Kelly W. Still | Agent(s): Solakian; J. S. | Examiner(s): Beausoliel, Jr.; Robert W. A method allowing the gradual deployment of a new security policy on a data processing system wherein users may access certain objects under the former authorization until complete security impleme...

Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies U.S. Patent US6085276 | Filed: 10/24/1997 | Issued: 07/04/2000 Assignee(s): Compaq Computers Corporation | Inventor(s): Stephen R. VanDoren + 1 | Agent(s): Williams Morgan & Amerson | Examiner(s): Meng-Ai T. An An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch...

Method and apparatus for operating an adaptive multiplexed address and data bus within a computer system U.S. Patent US6209053 | Filed: 08/28/1998 | Issued: 03/27/2001 Assignee(s): Intel Corporation | Inventor(s): Tsvika Kurts | Agent(s): Blakely, Sokoloff, Taylor & Zafman LLP | Examiner(s): Ario Etienne An apparatus, for operating a multiplexed 128-bit external bus within a computer system, includes arbitration logic that arbitrates between contending address and data requests according to the num...

Configurable weighted round robin arbiter U.S. Patent US6032218 | Filed: 05/28/1998 | Issued: 02/29/2000 Assignee(s): 3Com Corporation | Inventor(s): Amit Lewin + 1 | Agent(s): Weitz; David J.Wilson Sonsini Goodrich & Rosati | Examiner(s): Gopal C. Ray A configurable weighted round robin arbitration mechanism adapted to receive as input a vector of order N, wherein each bit in the vector represents the eligibility of a queue or other source of da...

Resource management system having a control structure to indicate the availability of integer from an integer pool upon responsive to a request U.S. Patent US6233630 | Filed: 04/12/1999 | Issued: 05/15/2001 Assignee(s): International Business Machines Corporation | Inventor(s): George William Wilhelm, Jr. | Agent(s): Shelley M Beckstrand | Examiner(s): Thomas Lee A system and method for managing access by a user to a reusable resource. An integer pool is provided, along with program and hardware structures for obtaining an integer from the integer pool, for...

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